drv8353s.h File Reference

Detailed Description

Contains public interface to various functions related to the DRV8353 object.

#include <math.h>
#include "spi.h"
#include "gpio.h"

Data Structures
struct	DRV8353_STAT00_BITS
	Object for the DRV8353 STATUS00 register. More...

union	DRV8353_STAT00_REG

struct	DRV8353_STAT01_BITS
	Object for the DRV8353 STATUS01 register. More...

union	DRV8353_STAT01_REG

struct	DRV8353_CTRL02_BITS
	Object for the DRV8353 CTRL02 register. More...

union	DRV8353_CTRL02_REG

struct	DRV8353_CTRL03_BITS
	Object for the DRV8353 CTRL03 register. More...

union	DRV8353_CTRL03_REG

struct	DRV8353_CTRL04_BITS
	Object for the DRV8353 CTRL04 register. More...

union	DRV8353_CTRL04_REG

struct	DRV8353_CTRL05_BITS
	Object for the DRV8353 CTRL05 register. More...

union	DRV8353_CTRL05_REG

struct	DRV8353_CTRL06_BITS
	Object for the DRV8353 CTRL06 register. More...

union	DRV8353_CTRL06_REG

struct	DRV8353_CTRL07_BITS
	Object for the DRV8353 CTRL06 register. More...

union	DRV8353_CTRL07_REG

struct	_DRV8353_VARS_t_
	Object for the DRV8353 registers and commands. More...

struct	_DRV8353_Obj_
	Defines the DRV8353 object. More...

Macros
#define	DRV8353_ADDR_MASK (0x7800)
	Defines the address mask. More...

#define	DRV8353_DATA_MASK (0x07FF)
	Defines the data mask. More...

#define	DRV8353_RW_MASK (0x8000)
	Defines the R/W mask. More...

#define	statReg00_addr 0x00
	Defines the register address. More...

#define	statReg01_addr 0x01

#define	ctrlReg02_addr 0x02

#define	ctrlReg03_addr 0x03

#define	ctrlReg04_addr 0x04

#define	ctrlReg05_addr 0x05

#define	ctrlReg06_addr 0x06

#define	ctrlReg07_addr 0x07

#define	DRV8353_FAULT_TYPE_MASK (0x07FF)
	Defines the R/W mask. More...

#define	DRV8353_STATUS00_VDS_LC_BITS (1 << 0)

#define	DRV8353_STATUS00_VDS_HC_BITS (1 << 1)

#define	DRV8353_STATUS00_VDS_LB_BITS (1 << 2)

#define	DRV8353_STATUS00_VDS_HB_BITS (1 << 3)

#define	DRV8353_STATUS00_VDS_LA_BITS (1 << 4)

#define	DRV8353_STATUS00_VDS_HA_BITS (1 << 5)

#define	DRV8353_STATUS00_OTSD_BITS (1 << 6)
	Defines the location of the OTSD (Over temperature shutdown) bits in the Status 1 register. More...

#define	DRV8353_STATUS00_UVLO_BITS (1 << 7)

#define	DRV8353_STATUS00_GDF_BITS (1 << 8)

#define	DRV8353_STATUS00_VDS_OCP_BITS (1 << 9)

#define	DRV8353_STATUS00_FAULT_BITS (1 << 10)

#define	DRV8353_STATUS01_VGS_LC_BITS (1 << 0)
	Defines the location of the VGS_LC bits in the Status 2 register. More...

#define	DRV8353_STATUS01_VGS_HC_BITS (1 << 1)
	Defines the location of the VGS_HC bits in the Status 2 register. More...

#define	DRV8353_STATUS01_VGS_LB_BITS (1 << 2)
	Defines the location of the VGS_LB bits in the Status 2 register. More...

#define	DRV8353_STATUS01_VGS_HB_BITS (1 << 3)
	Defines the location of the VGS_HB bits in the Status 2 register. More...

#define	DRV8353_STATUS01_VGS_LA_BITS (1 << 4)
	Defines the location of the VGS_LA bits in the Status 2 register. More...

#define	DRV8353_STATUS01_VGS_HA_BITS (1 << 5)
	Defines the location of the VGS_HA bits in the Status 2 register. More...

#define	DRV8353_STATUS01_CPUV_BITS (1 << 6)
	Defines the location of the CPUV (charge pump undervoltage) bits in the Status 2 register. More...

#define	DRV8353_STATUS01_OTW_BITS (1 << 7)
	Defines the location of the OTW bits in the Status 2 register. More...

#define	DRV8353_STATUS01_SC_OC_BITS (1 << 8)
	Defines the location of the SC_OC bits in the Status 2 register. More...

#define	DRV8353_STATUS01_SB_OC_BITS (1 << 9)
	Defines the location of the SB_OC bits in the Status 2 register. More...

#define	DRV8353_STATUS01_SA_OC_BITS (1 << 10)
	Defines the location of the SA_OC bits in the Status 2 register. More...

#define	DRV8353_CTRL02_CLR_FLT_BITS (1 << 0)
	Defines the location of the CLR_FLT bits in the Control 2 register. More...

#define	DRV8353_CTRL02_BRAKE_BITS (1 << 1)
	Defines the location of the BRAKE bits in the Control 2 register. More...

#define	DRV8353_CTRL02_COAST_BITS (1 << 2)
	Defines the location of the COAST bits in the Control 2 register. More...

#define	DRV8353_CTRL02_PWM1_DIR_BITS (1 << 3)
	Defines the location of the 1PWM_DIR bits in the Control 2 register. More...

#define	DRV8353_CTRL02_PWM1_COM_BITS (1 << 4)
	Defines the location of the 1PWM_COM bits in the Control 2 register. More...

#define	DRV8353_CTRL02_PWM_MODE_BITS (3 << 5)
	Defines the location of the PWM_MODE bits in the Control 2 register. More...

#define	DRV8353_CTRL02_OTW_REP_BITS (1 << 7)
	Defines the location of the OTW_REP bits in the Control 2 register. More...

#define	DRV8353_CTRL02_DIS_GDF_BITS (1 << 8)
	Defines the location of the DIS_GDF bits in the Control 2 register. More...

#define	DRV8353_CTRL02_DIS_CPUV_BITS (1 << 9)
	Defines the location of the DIS_CPUV bits in the Control 2 register. More...

#define	DRV8353_CTRL02_RESERVED1_BITS (1 << 10)
	Defines the location of the RESERVED1 bits in the Control 2 register. More...

#define	DRV8353_CTRL03_IDRIVEN_HS_BITS (15 << 0)
	Defines the location of the IDRIVEN_HS bits in the Control 3 register. More...

#define	DRV8353_CTRL03_IDRIVEP_HS_BITS (15 << 4)
	Defines the location of the IDRIVEP_HS bits in the Control 3 register. More...

#define	DRV8353_CTRL03_LOCK_BITS (7 << 8)
	Defines the location of the LOCK bits in the Control 3 register. More...

#define	DRV8353_CTRL04_IDRIVEN_LS_BITS (15 << 0)
	Defines the location of the IDRIVEN_LS bits in the Control 4 register. More...

#define	DRV8353_CTRL04_IDRIVEP_LS_BITS (15 << 4)
	Defines the location of the IDRIVEP_LS bits in the Control 4 register. More...

#define	DRV8353_CTRL04_TDRIVE_BITS (3 << 8)
	Defines the location of the TDRIVE bits in the Control 4 register. More...

#define	DRV8353_CTRL04_CBC_BITS (1 << 10)
	Defines the location of the CBC bits in the Control 4 register. More...

#define	DRV8353_CTRL05_VDS_LVL_BITS (15 << 0)
	Defines the location of the VDS_LVL bits in the Control 5 register. More...

#define	DRV8353_CTRL05_OCP_DEG_BITS (3 << 4)
	Defines the location of the OCP_DEG bits in the Control 5 register. More...

#define	DRV8353_CTRL05_OCP_MODE_BITS (3 << 6)
	Defines the location of the OCP_MODE bits in the Control 5 register. More...

#define	DRV8353_CTRL05_DEAD_TIME_BITS (3 << 8)
	Defines the location of the DEAD_TIME bits in the Control 5 register. More...

#define	DRV8353_CTRL05_TRETRY_BITS (1 << 10)
	Defines the location of the TRETRY bits in the Control 5 register. More...

#define	DRV8353_CTRL06_SEN_LVL_BITS (3 << 0)
	Defines the location of the SEN_LVL bits in the Control 6 register. More...

#define	DRV8353_CTRL06_CSA_CAL_C_BITS (1 << 2)
	Defines the location of the CSA_CAL_C bits in the Control 6 register. More...

#define	DRV8353_CTRL06_CSA_CAL_B_BITS (1 << 3)
	Defines the location of the CSA_CAL_B bits in the Control 6 register. More...

#define	DRV8353_CTRL06_CSA_CAL_A_BITS (1 << 4)
	Defines the location of the CSA_CAL_A bits in the Control 6 register. More...

#define	DRV8353_CTRL06_DIS_SEN_BITS (1 << 5)
	Defines the location of the DIS_SEN bits in the Control 6 register. More...

#define	DRV8353_CTRL06_CSA_GAIN_BITS (3 << 6)
	Defines the location of the CSA_GAIN bits in the Control 6 register. More...

#define	DRV8353_CTRL06_LS_REF_BITS (1 << 8)
	Defines the location of the LS_REF bits in the Control 6 register. More...

#define	DRV8353_CTRL06_VREF_DIV_BITS (1 << 9)
	Defines the location of the VREF_DIV bits in the Control 6 register. More...

#define	DRV8353_CTRL06_CSA_FET_BITS (1 << 10)
	Defines the location of the CSA_FET bits in the Control 6 register. More...

#define	DRV8353_CTRL07_CAL_MODE_BITS (1 << 0)
	Defines the location of the CAL_MODE bits in the Control 7 register. More...

Typedefs
typedef struct _DRV8353_VARS_t_	DRV8353_VARS_t
	Object for the DRV8353 registers and commands. More...

typedef struct _DRV8353_VARS_t_ *	DRV8353VARS_Handle
	Defines the DRV8353_VARS_t handle. More...

typedef struct _DRV8353_Obj_	DRV8353_Obj
	Defines the DRV8353 object. More...

typedef struct _DRV8353_Obj_ *	DRV8353_Handle
	Defines the DRV8353 handle. More...

typedef uint16_t	DRV_Word_t
	Defines the DRV8353 Word type. More...

Enumerations
enum	DRV8353_CtrlMode_e { DRV8353_CTRLMODE_WRITE = 0, DRV8353_CTRLMODE_READ = 1 }
	Enumeration for the R/W modes. More...

enum	DRV8353_Address_e { DRV8353_ADDRESS_STATUS_0 = (0 << 11), DRV8353_ADDRESS_STATUS_1 = (1 << 11), DRV8353_ADDRESS_CONTROL_2 = (2 << 11), DRV8353_ADDRESS_CONTROL_3 = (3 << 11), DRV8353_ADDRESS_CONTROL_4 = (4 << 11), DRV8353_ADDRESS_CONTROL_5 = (5 << 11), DRV8353_ADDRESS_CONTROL_6 = (6 << 11), DRV8353_ADDRESS_CONTROL_7 = (7 << 11) }
	Enumeration for the register addresses. More...

enum	DRV8353_STATUS00_WarningWatchdog_e { DRV8353_VDS_LC = (1 << 0), DRV8353_VDS_HC = (1 << 1), DRV8353_VDS_LB = (1 << 2), DRV8353_VDS_HB = (1 << 3), DRV8353_VDS_LA = (1 << 4), DRV8353_VDS_HA = (1 << 5), DRV8353_OTSD = (1 << 6), DRV8353_UVLO = (1 << 7), DRV8353_GDF = (1 << 8), DRV8353_VDS_OCP = (1 << 9), DRV8353_FAULT = (1 << 10) }
	Enumeration for the Status 0 register, faults. More...

enum	DRV8353_STATUS01_OvVdsFaults_e { DRV8353_VGS_LC = (1 << 0), DRV8353_VGS_HC = (1 << 1), DRV8353_VGS_LB = (1 << 2), DRV8353_VGS_HB = (1 << 3), DRV8353_VGS_LA = (1 << 4), DRV8353_VGS_HA = (1 << 5), DRV8353_CPUV = (1 << 6), DRV8353_OTW = (1 << 7), DRV8353_SC_OC = (1 << 8), DRV8353_SB_OC = (1 << 9), DRV8353_SA_OC = (1 << 10) }
	Enumeration for the Status 1 register, OV/VDS faults. More...

enum	DRV8353_CTRL02_PWMMode_e { DRV8353_PWMMODE_6 = 0, DRV8353_PWMMODE_3 = 1, DRV8353_PWMMODE_1 = 2 }
	Enumeration for the driver PWM mode. More...

enum	DRV8353_CTRL03_PeakSourCurHS_e { DRV8353_ISOUR_HS_0P010_A = 0, DRV8353_ISOUR_HS_0P030_A = 1, DRV8353_ISOUR_HS_0P060_A = 2, DRV8353_ISOUR_HS_0P080_A = 3, DRV8353_ISOUR_HS_0P120_A = 4, DRV8353_ISOUR_HS_0P140_A = 5, DRV8353_ISOUR_HS_0P170_A = 6, DRV8353_ISOUR_HS_0P190_A = 7, DRV8353_ISOUR_HS_0P260_A = 8, DRV8353_ISOUR_HS_0P330_A = 9, DRV8353_ISOUR_HS_0P370_A = 10, DRV8353_ISOUR_HS_0P440_A = 11, DRV8353_ISOUR_HS_0P570_A = 12, DRV8353_ISOUR_HS_0P680_A = 13, DRV8353_ISOUR_HS_0P820_A = 14, DRV8353_ISOUR_HS_1P000_A = 15 }
	Enumeration for the high side gate drive peak source current; gate currents not consistent with DS. More...

enum	DRV8353_CTRL03_PeakSinkCurHS_e { DRV8353_ISINK_HS_0P020_A = 0, DRV8353_ISINK_HS_0P060_A = 1, DRV8353_ISINK_HS_0P120_A = 2, DRV8353_ISINK_HS_0P160_A = 3, DRV8353_ISINK_HS_0P240_A = 4, DRV8353_ISINK_HS_0P280_A = 5, DRV8353_ISINK_HS_0P340_A = 6, DRV8353_ISINK_HS_0P380_A = 7, DRV8353_ISINK_HS_0P520_A = 8, DRV8353_ISINK_HS_0P660_A = 9, DRV8353_ISINK_HS_0P740_A = 10, DRV8353_ISINK_HS_0P880_A = 11, DRV8353_ISINK_HS_1P140_A = 12, DRV8353_ISINK_HS_1P360_A = 13, DRV8353_ISINK_HS_1P640_A = 14, DRV8353_ISINK_HS_2P000_A = 15 }
	Enumeration for the high side gate drive peak sink current; gate currents not consistent with DS. More...

enum	DRV8353_CTRL03_Lock_e { DRV8353_LOCK_UNLOCK = 3, DRV8353_LOCK_LOCK = 6 }
	Enumeration for the high side and low side gate drive peak source time; adapt timings to DRV8353. More...

enum	DRV8353_CTRL04_PeakTime_e { DRV8353_TSOUR_500_NS = 0, DRV8353_TSOUR_1000_NS = 1, DRV8353_TSOUR_2000_NS = 2, DRV8353_TSOUR_4000_NS = 3 }
	Enumeration for the high side and low side gate drive peak source time; adapt timings to DRV8353. More...

enum	DRV8353_CTRL04_PeakSourCurLS_e { DRV8353_ISOUR_LS_0P010_A = 0, DRV8353_ISOUR_LS_0P030_A = 1, DRV8353_ISOUR_LS_0P060_A = 2, DRV8353_ISOUR_LS_0P080_A = 3, DRV8353_ISOUR_LS_0P120_A = 4, DRV8353_ISOUR_LS_0P140_A = 5, DRV8353_ISOUR_LS_0P170_A = 6, DRV8353_ISOUR_LS_0P190_A = 7, DRV8353_ISOUR_LS_0P260_A = 8, DRV8353_ISOUR_LS_0P330_A = 9, DRV8353_ISOUR_LS_0P370_A = 10, DRV8353_ISOUR_LS_0P440_A = 11, DRV8353_ISOUR_LS_0P570_A = 12, DRV8353_ISOUR_LS_0P680_A = 13, DRV8353_ISOUR_LS_0P820_A = 14, DRV8353_ISOUR_LS_1P000_A = 15 }
	Enumeration for the low side gate drive peak source current; adapt current ratings. More...

enum	DRV8353_CTRL04_PeakSinkCurLS_e { DRV8353_ISINK_LS_0P020_A = 0, DRV8353_ISINK_LS_0P060_A = 1, DRV8353_ISINK_LS_0P120_A = 2, DRV8353_ISINK_LS_0P160_A = 3, DRV8353_ISINK_LS_0P240_A = 4, DRV8353_ISINK_LS_0P280_A = 5, DRV8353_ISINK_LS_0P340_A = 6, DRV8353_ISINK_LS_0P380_A = 7, DRV8353_ISINK_LS_0P520_A = 8, DRV8353_ISINK_LS_0P660_A = 9, DRV8353_ISINK_LS_0P740_A = 10, DRV8353_ISINK_LS_0P880_A = 11, DRV8353_ISINK_LS_1P140_A = 12, DRV8353_ISINK_LS_1P360_A = 13, DRV8353_ISINK_LS_1P640_A = 14, DRV8353_ISINK_LS_2P000_A = 15 }
	Enumeration for the low side gate drive peak sink current; adapt current ratings. More...

enum	DRV8353_CTRL05_VDSLVL_e { DRV8353_VDS_LEVEL_0P060_V = 0, DRV8353_VDS_LEVEL_0P130_V = 1, DRV8353_VDS_LEVEL_0P200_V = 2, DRV8353_VDS_LEVEL_0P260_V = 3, DRV8353_VDS_LEVEL_0P310_V = 4, DRV8353_VDS_LEVEL_0P450_V = 5, DRV8353_VDS_LEVEL_0P530_V = 6, DRV8353_VDS_LEVEL_0P600_V = 7, DRV8353_VDS_LEVEL_0P680_V = 8, DRV8353_VDS_LEVEL_0P750_V = 9, DRV8353_VDS_LEVEL_0P940_V = 10, DRV8353_VDS_LEVEL_1P130_V = 11, DRV8353_VDS_LEVEL_1P300_V = 12, DRV8353_VDS_LEVEL_1P500_V = 13, DRV8353_VDS_LEVEL_1P700_V = 14, DRV8353_VDS_LEVEL_1P880_V = 15 }
	Enumeration for the VDS comparator threshold. More...

enum	DRV8353_CTRL05_OcpDeg_e { DRV8353_VDSDEG_2_US = 0, DRV8353_VDSDEG_4_US = 1, DRV8353_VDSDEG_6_US = 2, DRV8353_VDSDEG_8_US = 3 }
	Enumeration for the OCP/VDS sense deglitch time; adapt deglitch time comments. More...

enum	DRV8353_CTRL05_OcpMode_e { DRV8353_LATCHED_SHUTDOWN = 0, DRV8353_AUTOMATIC_RETRY = 1, DRV8353_REPORT_ONLY = 2, DRV8353_DISABLE_OCP = 3 }
	Enumeration for the OCP report mode. More...

enum	DRV8353_CTRL05_DeadTime_e { DRV8353_DEADTIME_50_NS = 0, DRV8353_DEADTIME_100_NS = 1, DRV8353_DEADTIME_200_NS = 2, DRV8353_DEADTIME_400_NS = 3 }
	Enumeration for the driver dead time. More...

enum	DRV8353_CTRL06_SENLevel_e { DRV8353_SEN_Lvl_Ocp_0p25 = 0, DRV8353_SEN_Lvl_Ocp_0p50 = 1, DRV8353_SEN_Lvl_Ocp_0p75 = 2, DRV8353_SEN_Lvl_Ocp_1p00 = 3 }
	Enumeration for the Sense OCP level. More...

enum	DRV8353_CTRL06_CSAGain_e { DRV8353_Gain_5VpV = 0, DRV8353_Gain_10VpV = 1, DRV8353_Gain_20VpV = 2, DRV8353_Gain_40VpV = 3 }
	Enumeration for the gain of shunt amplifier. More...

Functions
DRV8353_Handle	DRV8353_init (void *pMemory)
	Initializes the DRV8353 object. More...

static DRV_Word_t	DRV8353_buildCtrlWord (const DRV8353_CtrlMode_e ctrlMode, const DRV8353_Address_e regAddr, const uint16_t data)
	Builds the control word. More...

void	DRV8353_enable (DRV8353_Handle handle)
	Enables the DRV8353. More...

void	DRV8353_setSPIHandle (DRV8353_Handle handle, uint32_t spiHandle)
	Sets the SPI handle in the DRV8353. More...

void	DRV8353_setGPIOCSNumber (DRV8353_Handle handle, uint32_t gpioNumber)
	Sets the GPIO number in the DRV8353. More...

void	DRV8353_setGPIOENNumber (DRV8353_Handle handle, uint32_t gpioNumber)
	Sets the GPIO number in the DRV8353. More...

static void	DRV8353_resetEnableTimeout (DRV8353_Handle handle)
	Resets the enable timeout flag. More...

static void	DRV8353_resetRxTimeout (DRV8353_Handle handle)
	Resets the RX fifo timeout flag. More...

void	DRV8353_setupSPI (DRV8353_Handle handle, DRV8353_VARS_t *drv8353Vars)
	Initialize the interface to all 8320 SPI variables. More...

uint16_t	DRV8353_readSPI (DRV8353_Handle handle, const DRV8353_Address_e regAddr)
	Reads data from the DRV8353 register. More...

void	DRV8353_writeSPI (DRV8353_Handle handle, const DRV8353_Address_e regAddr, const uint16_t data)
	Writes data to the DRV8353 register. More...

void	DRV8353_writeData (DRV8353_Handle handle, DRV8353_VARS_t *drv8353Vars)
	Write to the DRV8353 SPI registers. More...

void	DRV8353_readData (DRV8353_Handle handle, DRV8353_VARS_t *drv8353Vars)
	Read from the DRV8353 SPI registers. More...

Detailed Description

Data Structures

Macros

Typedefs

Enumerations

Functions