drv8353s.h

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//#############################################################################
// $TI Release: MotorControl SDK v4.01.00.00 $
// $Release Date: Mon Mar 11 18:37:41 CDT 2019 $
// $Copyright:
// Copyright (C) 2017-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
//
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the
//   distribution.
//
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
 
 
 
 
#ifndef DRV8353S_H
#define DRV8353S_H
 
 
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
 
//*****************************************************************************
//
//
//*****************************************************************************
 
// the includes
#include <math.h>
 
// drivers
#include "spi.h"
#include "gpio.h"
 
// **************************************************************************
// modules
 
// **************************************************************************
// solutions
 
// **************************************************************************
// the defines
 
#define DRV8353_ADDR_MASK                   (0x7800)
 
#define DRV8353_DATA_MASK                   (0x07FF)
 
#define DRV8353_RW_MASK                     (0x8000)
 
#define statReg00_addr      0x00
#define statReg01_addr      0x01
#define ctrlReg02_addr      0x02
#define ctrlReg03_addr      0x03
#define ctrlReg04_addr      0x04
#define ctrlReg05_addr      0x05
#define ctrlReg06_addr      0x06
#define ctrlReg07_addr      0x07
 
//
// STATUS00
//
#define DRV8353_FAULT_TYPE_MASK             (0x07FF)
 
#define DRV8353_STATUS00_VDS_LC_BITS        (1 << 0)
#define DRV8353_STATUS00_VDS_HC_BITS        (1 << 1)
#define DRV8353_STATUS00_VDS_LB_BITS        (1 << 2)
#define DRV8353_STATUS00_VDS_HB_BITS        (1 << 3)
#define DRV8353_STATUS00_VDS_LA_BITS        (1 << 4)
#define DRV8353_STATUS00_VDS_HA_BITS        (1 << 5)
 
#define DRV8353_STATUS00_OTSD_BITS          (1 << 6)
#define DRV8353_STATUS00_UVLO_BITS          (1 << 7)
#define DRV8353_STATUS00_GDF_BITS           (1 << 8)
#define DRV8353_STATUS00_VDS_OCP_BITS       (1 << 9)
#define DRV8353_STATUS00_FAULT_BITS         (1 << 10)
 
//
// STATUS01
//
#define DRV8353_STATUS01_VGS_LC_BITS        (1 << 0)
 
#define DRV8353_STATUS01_VGS_HC_BITS        (1 << 1)
 
#define DRV8353_STATUS01_VGS_LB_BITS        (1 << 2)
 
#define DRV8353_STATUS01_VGS_HB_BITS        (1 << 3)
 
#define DRV8353_STATUS01_VGS_LA_BITS        (1 << 4)
 
#define DRV8353_STATUS01_VGS_HA_BITS        (1 << 5)
 
#define DRV8353_STATUS01_CPUV_BITS          (1 << 6)
 
#define DRV8353_STATUS01_OTW_BITS           (1 << 7)
 
#define DRV8353_STATUS01_SC_OC_BITS         (1 << 8)
 
#define DRV8353_STATUS01_SB_OC_BITS         (1 << 9)
 
#define DRV8353_STATUS01_SA_OC_BITS         (1 << 10)
 
//
// CTRL02
//
#define DRV8353_CTRL02_CLR_FLT_BITS         (1 << 0)
 
#define DRV8353_CTRL02_BRAKE_BITS           (1 << 1)
 
#define DRV8353_CTRL02_COAST_BITS           (1 << 2)
 
#define DRV8353_CTRL02_PWM1_DIR_BITS        (1 << 3)
 
#define DRV8353_CTRL02_PWM1_COM_BITS        (1 << 4)
 
#define DRV8353_CTRL02_PWM_MODE_BITS        (3 << 5)
 
#define DRV8353_CTRL02_OTW_REP_BITS         (1 << 7)
 
#define DRV8353_CTRL02_DIS_GDF_BITS         (1 << 8)
 
#define DRV8353_CTRL02_DIS_CPUV_BITS        (1 << 9)
 
#define DRV8353_CTRL02_RESERVED1_BITS       (1 << 10)
 
//
// CTRL03
//
#define DRV8353_CTRL03_IDRIVEN_HS_BITS      (15 << 0)
 
#define DRV8353_CTRL03_IDRIVEP_HS_BITS      (15 << 4)
 
#define DRV8353_CTRL03_LOCK_BITS            (7 << 8)
 
//
// CTRL04
//
#define DRV8353_CTRL04_IDRIVEN_LS_BITS      (15 << 0)
 
#define DRV8353_CTRL04_IDRIVEP_LS_BITS      (15 << 4)
 
#define DRV8353_CTRL04_TDRIVE_BITS          (3 << 8)
 
#define DRV8353_CTRL04_CBC_BITS             (1 << 10)
 
//
// CTRL05
//
#define DRV8353_CTRL05_VDS_LVL_BITS         (15 << 0)
 
#define DRV8353_CTRL05_OCP_DEG_BITS         (3 << 4)
 
#define DRV8353_CTRL05_OCP_MODE_BITS        (3 << 6)
 
#define DRV8353_CTRL05_DEAD_TIME_BITS       (3 << 8)
 
#define DRV8353_CTRL05_TRETRY_BITS          (1 << 10)
 
//
// CTRL06
//
#define DRV8353_CTRL06_SEN_LVL_BITS         (3 << 0)
 
#define DRV8353_CTRL06_CSA_CAL_C_BITS       (1 << 2)
 
#define DRV8353_CTRL06_CSA_CAL_B_BITS       (1 << 3)
 
#define DRV8353_CTRL06_CSA_CAL_A_BITS       (1 << 4)
 
#define DRV8353_CTRL06_DIS_SEN_BITS         (1 << 5)
 
#define DRV8353_CTRL06_CSA_GAIN_BITS        (3 << 6)
 
#define DRV8353_CTRL06_LS_REF_BITS          (1 << 8)
 
#define DRV8353_CTRL06_VREF_DIV_BITS        (1 << 9)
 
#define DRV8353_CTRL06_CSA_FET_BITS         (1 << 10)
 
 
//
// CTRL06
//
#define DRV8353_CTRL07_CAL_MODE_BITS         (1 << 0)
// **************************************************************************
// the typedefs
 
//------------------------------------------------------------------------------
typedef enum
{
    DRV8353_CTRLMODE_WRITE    = 0,  
    DRV8353_CTRLMODE_READ     = 1   
} DRV8353_CtrlMode_e;
 
typedef enum
{
    DRV8353_ADDRESS_STATUS_0  = (0 << 11),  
    DRV8353_ADDRESS_STATUS_1  = (1 << 11),  
    DRV8353_ADDRESS_CONTROL_2 = (2 << 11),  
    DRV8353_ADDRESS_CONTROL_3 = (3 << 11),  
    DRV8353_ADDRESS_CONTROL_4 = (4 << 11),  
    DRV8353_ADDRESS_CONTROL_5 = (5 << 11),  
    DRV8353_ADDRESS_CONTROL_6 = (6 << 11),  
    DRV8353_ADDRESS_CONTROL_7 = (7 << 11)   
} DRV8353_Address_e;
 
typedef enum
{
    DRV8353_VDS_LC      = (1 << 0),    
    DRV8353_VDS_HC      = (1 << 1),    
    DRV8353_VDS_LB      = (1 << 2),    
    DRV8353_VDS_HB      = (1 << 3),    
    DRV8353_VDS_LA      = (1 << 4),    
    DRV8353_VDS_HA      = (1 << 5),    
    DRV8353_OTSD        = (1 << 6),    
    DRV8353_UVLO        = (1 << 7),    
    DRV8353_GDF         = (1 << 8),    
    DRV8353_VDS_OCP     = (1 << 9),    
    DRV8353_FAULT       = (1 << 10)    
} DRV8353_STATUS00_WarningWatchdog_e;
 
typedef enum
{
    DRV8353_VGS_LC      = (1 << 0),    
    DRV8353_VGS_HC      = (1 << 1),    
    DRV8353_VGS_LB      = (1 << 2),    
    DRV8353_VGS_HB      = (1 << 3),    
    DRV8353_VGS_LA      = (1 << 4),    
    DRV8353_VGS_HA      = (1 << 5),    
    DRV8353_CPUV        = (1 << 6),    
    DRV8353_OTW         = (1 << 7),    
    DRV8353_SC_OC       = (1 << 8),    
    DRV8353_SB_OC       = (1 << 9),    
    DRV8353_SA_OC       = (1 << 10)    
} DRV8353_STATUS01_OvVdsFaults_e;
 
typedef enum
{
    DRV8353_PWMMODE_6 = 0,     
    DRV8353_PWMMODE_3 = 1,     
    DRV8353_PWMMODE_1 = 2      
} DRV8353_CTRL02_PWMMode_e;
 
typedef enum
{
    DRV8353_ISOUR_HS_0P010_A = 0,  
    DRV8353_ISOUR_HS_0P030_A = 1,  
    DRV8353_ISOUR_HS_0P060_A = 2,  
    DRV8353_ISOUR_HS_0P080_A = 3,  
    DRV8353_ISOUR_HS_0P120_A = 4,  
    DRV8353_ISOUR_HS_0P140_A = 5,  
    DRV8353_ISOUR_HS_0P170_A = 6,  
    DRV8353_ISOUR_HS_0P190_A = 7,  
    DRV8353_ISOUR_HS_0P260_A = 8,  
    DRV8353_ISOUR_HS_0P330_A = 9,  
    DRV8353_ISOUR_HS_0P370_A = 10, 
    DRV8353_ISOUR_HS_0P440_A = 11, 
    DRV8353_ISOUR_HS_0P570_A = 12, 
    DRV8353_ISOUR_HS_0P680_A = 13, 
    DRV8353_ISOUR_HS_0P820_A = 14, 
    DRV8353_ISOUR_HS_1P000_A = 15  
} DRV8353_CTRL03_PeakSourCurHS_e;
 
typedef enum
{
    DRV8353_ISINK_HS_0P020_A = 0,  
    DRV8353_ISINK_HS_0P060_A = 1,  
    DRV8353_ISINK_HS_0P120_A = 2,  
    DRV8353_ISINK_HS_0P160_A = 3,  
    DRV8353_ISINK_HS_0P240_A = 4,  
    DRV8353_ISINK_HS_0P280_A = 5,  
    DRV8353_ISINK_HS_0P340_A = 6,  
    DRV8353_ISINK_HS_0P380_A = 7,  
    DRV8353_ISINK_HS_0P520_A = 8,  
    DRV8353_ISINK_HS_0P660_A = 9,  
    DRV8353_ISINK_HS_0P740_A = 10, 
    DRV8353_ISINK_HS_0P880_A = 11, 
    DRV8353_ISINK_HS_1P140_A = 12, 
    DRV8353_ISINK_HS_1P360_A = 13, 
    DRV8353_ISINK_HS_1P640_A = 14, 
    DRV8353_ISINK_HS_2P000_A = 15  
} DRV8353_CTRL03_PeakSinkCurHS_e;
 
typedef enum
{
    DRV8353_LOCK_UNLOCK   = 3,           
    DRV8353_LOCK_LOCK     = 6,          
} DRV8353_CTRL03_Lock_e;
 
typedef enum
{
    DRV8353_TSOUR_500_NS  = 0,     
    DRV8353_TSOUR_1000_NS = 1,     
    DRV8353_TSOUR_2000_NS = 2,     
    DRV8353_TSOUR_4000_NS = 3      
} DRV8353_CTRL04_PeakTime_e;
 
typedef enum
{
    DRV8353_ISOUR_LS_0P010_A = 0,  
    DRV8353_ISOUR_LS_0P030_A = 1,  
    DRV8353_ISOUR_LS_0P060_A = 2,  
    DRV8353_ISOUR_LS_0P080_A = 3,  
    DRV8353_ISOUR_LS_0P120_A = 4,  
    DRV8353_ISOUR_LS_0P140_A = 5,  
    DRV8353_ISOUR_LS_0P170_A = 6,  
    DRV8353_ISOUR_LS_0P190_A = 7,  
    DRV8353_ISOUR_LS_0P260_A = 8,  
    DRV8353_ISOUR_LS_0P330_A = 9,  
    DRV8353_ISOUR_LS_0P370_A = 10, 
    DRV8353_ISOUR_LS_0P440_A = 11, 
    DRV8353_ISOUR_LS_0P570_A = 12, 
    DRV8353_ISOUR_LS_0P680_A = 13, 
    DRV8353_ISOUR_LS_0P820_A = 14, 
    DRV8353_ISOUR_LS_1P000_A = 15  
} DRV8353_CTRL04_PeakSourCurLS_e;
 
typedef enum
{
    DRV8353_ISINK_LS_0P020_A = 0,  
    DRV8353_ISINK_LS_0P060_A = 1,  
    DRV8353_ISINK_LS_0P120_A = 2,  
    DRV8353_ISINK_LS_0P160_A = 3,  
    DRV8353_ISINK_LS_0P240_A = 4,  
    DRV8353_ISINK_LS_0P280_A = 5,  
    DRV8353_ISINK_LS_0P340_A = 6,  
    DRV8353_ISINK_LS_0P380_A = 7,  
    DRV8353_ISINK_LS_0P520_A = 8,  
    DRV8353_ISINK_LS_0P660_A = 9,  
    DRV8353_ISINK_LS_0P740_A = 10, 
    DRV8353_ISINK_LS_0P880_A = 11, 
    DRV8353_ISINK_LS_1P140_A = 12, 
    DRV8353_ISINK_LS_1P360_A = 13, 
    DRV8353_ISINK_LS_1P640_A = 14, 
    DRV8353_ISINK_LS_2P000_A = 15  
} DRV8353_CTRL04_PeakSinkCurLS_e;
 
typedef enum
{
    DRV8353_VDS_LEVEL_0P060_V = 0,    
    DRV8353_VDS_LEVEL_0P130_V = 1,    
    DRV8353_VDS_LEVEL_0P200_V = 2,    
    DRV8353_VDS_LEVEL_0P260_V = 3,    
    DRV8353_VDS_LEVEL_0P310_V = 4,    
    DRV8353_VDS_LEVEL_0P450_V = 5,    
    DRV8353_VDS_LEVEL_0P530_V = 6,    
    DRV8353_VDS_LEVEL_0P600_V = 7,    
    DRV8353_VDS_LEVEL_0P680_V = 8,    
    DRV8353_VDS_LEVEL_0P750_V = 9,    
    DRV8353_VDS_LEVEL_0P940_V = 10,   
    DRV8353_VDS_LEVEL_1P130_V = 11,   
    DRV8353_VDS_LEVEL_1P300_V = 12,   
    DRV8353_VDS_LEVEL_1P500_V = 13,   
    DRV8353_VDS_LEVEL_1P700_V = 14,   
    DRV8353_VDS_LEVEL_1P880_V = 15    
} DRV8353_CTRL05_VDSLVL_e;
 
typedef enum
{
    DRV8353_VDSDEG_2_US = 0,       
    DRV8353_VDSDEG_4_US = 1,       
    DRV8353_VDSDEG_6_US = 2,       
    DRV8353_VDSDEG_8_US = 3        
} DRV8353_CTRL05_OcpDeg_e;
 
typedef enum
{
    DRV8353_LATCHED_SHUTDOWN = 0,  
    DRV8353_AUTOMATIC_RETRY  = 1,  
    DRV8353_REPORT_ONLY      = 2,  
    DRV8353_DISABLE_OCP      = 3   
} DRV8353_CTRL05_OcpMode_e;
 
typedef enum
{
    DRV8353_DEADTIME_50_NS  = 0,   
    DRV8353_DEADTIME_100_NS = 1,   
    DRV8353_DEADTIME_200_NS = 2,   
    DRV8353_DEADTIME_400_NS = 3    
} DRV8353_CTRL05_DeadTime_e;
 
typedef enum
{
    DRV8353_SEN_Lvl_Ocp_0p25 = 0,  
    DRV8353_SEN_Lvl_Ocp_0p50 = 1,  
    DRV8353_SEN_Lvl_Ocp_0p75 = 2,  
    DRV8353_SEN_Lvl_Ocp_1p00 = 3   
} DRV8353_CTRL06_SENLevel_e;
 
 
typedef enum
{
    DRV8353_Gain_5VpV  = 0,      
    DRV8353_Gain_10VpV = 1,      
    DRV8353_Gain_20VpV = 2,      
    DRV8353_Gain_40VpV = 3       
} DRV8353_CTRL06_CSAGain_e;
 
//------------------------------------------------------------------------------
struct DRV8353_STAT00_BITS {                    // bits description
    bool                VDS_LC:1;         // Bits 0
    bool                VDS_HC:1;         // Bits 1
    bool                VDS_LB:1;         // Bits 2
    bool                VDS_HB:1;         // Bits 3
    bool                VDS_LA:1;         // Bits 4
    bool                VDS_HA:1;         // Bits 5
    bool                OTSD:1;           // Bits 6
    bool                UVLO:1;           // Bits 7
    bool                GDF:1;            // Bits 8
    bool                VDS_OCP:1;        // Bits 9
    bool                FAULT:1;          // Bits 10
    uint16_t            rsvd2:5;          // 15:11 Reserved
};
 
union DRV8353_STAT00_REG
{
    uint16_t all;
    struct   DRV8353_STAT00_BITS bit;
};
 
struct DRV8353_STAT01_BITS {                    // bits description
    bool                VGS_LC:1;         // Bits 0
    bool                VGS_HC:1;         // Bits 1
    bool                VGS_LB:1;         // Bits 2
    bool                VGS_HB:1;         // Bits 3
    bool                VGS_LA:1;         // Bits 4
    bool                VGS_HA:1;         // Bits 5
    bool                CPUV:1;           // Bits 6
    bool                OTW:1;            // Bits 7
    bool                SC_OC:1;          // Bits 8
    bool                SB_OC:1;          // Bits 9
    bool                SA_OC:1;          // Bits 10
    uint16_t            rsvd2:5;          // 15:11 Reserved
};
 
union DRV8353_STAT01_REG
{
    uint16_t all;
    struct   DRV8353_STAT01_BITS bit;
};
 
struct DRV8353_CTRL02_BITS {                    // bits description
    bool                        CLR_FLT:1;        // Bits 0
    bool                        BRAKE:1;          // Bits 1
    bool                        COAST:1;          // Bits 2
    bool                        PWM1_DIR:1;       // Bits 3
    bool                        PWM1_COM:1;       // Bits 4
    DRV8353_CTRL02_PWMMode_e    PWM_MODE:2;       // Bits 6-5
    bool                        OTW_REP:1;        // Bits 7
    bool                        DIS_GDF:1;        // Bits 8
    bool                        DIS_GPUV:1;       // Bits 9
    bool                        OCP_ACT:1;        // Bits 10
    uint16_t                    rsvd2:5;          // 15:11 Reserved
};
 
union DRV8353_CTRL02_REG
{
    uint16_t all;
    struct   DRV8353_CTRL02_BITS bit;
};
 
struct DRV8353_CTRL03_BITS {                    // bits description
    DRV8353_CTRL03_PeakSinkCurHS_e  IDRIVEN_HS:4;     // Bits 3-0
    DRV8353_CTRL03_PeakSourCurHS_e  IDRIVEP_HS:4;     // Bits 7-4
    DRV8353_CTRL03_Lock_e           LOCK:3;           // Bits 10-8
    uint16_t                        rsvd:5;           // 15:11 Reserved
};
 
union DRV8353_CTRL03_REG
{
    uint16_t all;
    struct   DRV8353_CTRL03_BITS bit;
};
 
struct DRV8353_CTRL04_BITS {                    // bits description
    DRV8353_CTRL04_PeakSinkCurLS_e  IDRIVEN_LS:4;     // Bits 3-0
    DRV8353_CTRL04_PeakSourCurLS_e  IDRIVEP_LS:4;     // Bits 7-4
    DRV8353_CTRL04_PeakTime_e       TDRIVE:2;         // Bits 9-8
    bool                            CBC:1;            // Bits 10
    uint16_t                        rsvd:5;           // 15:11 Reserved
};
 
union DRV8353_CTRL04_REG
{
    uint16_t all;
    struct   DRV8353_CTRL04_BITS bit;
};
 
struct DRV8353_CTRL05_BITS {                    // bits description
    DRV8353_CTRL05_VDSLVL_e     VDS_LVL:4;        // Bits 3-0
    DRV8353_CTRL05_OcpDeg_e     OCP_DEG:2;        // Bits 5-4
    DRV8353_CTRL05_OcpMode_e    OCP_MODE:2;       // Bits 7-6
    DRV8353_CTRL05_DeadTime_e   DEAD_TIME:2;      // Bits 9-8
    bool                        TRETRY:1;         // Bits 10
    uint16_t                    rsvd:5;           // 15:11 Reserved
};
 
union DRV8353_CTRL05_REG
{
    uint16_t all;
    struct   DRV8353_CTRL05_BITS bit;
};
 
struct DRV8353_CTRL06_BITS {                // bits description
    DRV8353_CTRL06_SENLevel_e   SEN_LVL:2;      // Bits 1-0
    bool                        CSA_CAL_C:1;    // Bits 2
    bool                        CSA_CAL_B:1;    // Bits 3
    bool                        CSA_CAL_A:1;    // Bits 4
    bool                        DIS_SEN:1;      // Bits 5
    DRV8353_CTRL06_CSAGain_e    CSA_GAIN:2;     // Bits 7-6
    bool                        LS_REF:1;       // Bits 8
    bool                        VREF_DIV:1;     // Bits 9
    bool                        CSA_FET:1;      // Bits 10
    uint16_t                    rsvd:5;         // 15:11 Reserved
};
 
union DRV8353_CTRL06_REG
{
    uint16_t all;
    struct   DRV8353_CTRL06_BITS bit;
};
 
struct DRV8353_CTRL07_BITS {                // bits description
    bool                        CAL_MODE:1;     // Bits 0
    uint16_t                    rsvd1:10;       // 10:1  Reserved
    uint16_t                    rsvd2:5;        // 15:11 Reserved
};
 
union DRV8353_CTRL07_REG
{
    uint16_t all;
    struct   DRV8353_CTRL07_BITS bit;
};
 
typedef struct _DRV8353_VARS_t_
{
    union DRV8353_STAT00_REG    statReg00;
    union DRV8353_STAT01_REG    statReg01;
 
    union DRV8353_CTRL02_REG    ctrlReg02;
    union DRV8353_CTRL03_REG    ctrlReg03;
    union DRV8353_CTRL04_REG    ctrlReg04;
    union DRV8353_CTRL05_REG    ctrlReg05;
    union DRV8353_CTRL06_REG    ctrlReg06;
    union DRV8353_CTRL07_REG    ctrlReg07;
 
    bool                writeCmd;
    bool                readCmd;
    uint16_t            manWriteAddr;
    uint16_t            manReadAddr;
    uint16_t            manWriteData;
    uint16_t            manReadData;
    bool                manWriteCmd;
    bool                manReadCmd;
}DRV8353_VARS_t;
 
typedef struct _DRV8353_VARS_t_ *DRV8353VARS_Handle;
 
typedef struct _DRV8353_Obj_
{
    uint32_t  spiHandle;     
    uint32_t  gpioNumber_CS; 
    uint32_t  gpioNumber_EN; 
    bool      rxTimeOut;     
    bool      enableTimeOut; 
} DRV8353_Obj;
 
typedef struct _DRV8353_Obj_ *DRV8353_Handle;
 
typedef  uint16_t    DRV_Word_t;
 
// **************************************************************************
// the globals
 
// **************************************************************************
// the function prototypes
 
extern DRV8353_Handle DRV8353_init(void *pMemory);
 
static inline DRV_Word_t DRV8353_buildCtrlWord(
                                            const DRV8353_CtrlMode_e ctrlMode,
                                            const DRV8353_Address_e regAddr,
                                            const uint16_t data)
{
    DRV_Word_t ctrlWord = ctrlMode | regAddr | (data & DRV8353_DATA_MASK);
 
    return(ctrlWord);
} // end of DRV8353_buildCtrlWord() function
 
extern void DRV8353_enable(DRV8353_Handle handle);
 
void DRV8353_setSPIHandle(DRV8353_Handle handle,uint32_t spiHandle);
 
void DRV8353_setGPIOCSNumber(DRV8353_Handle handle,uint32_t gpioNumber);
 
void DRV8353_setGPIOENNumber(DRV8353_Handle handle,uint32_t gpioNumber);
 
static inline void DRV8353_resetEnableTimeout(DRV8353_Handle handle)
{
    DRV8353_Obj *obj = (DRV8353_Obj *)handle;
 
    obj->enableTimeOut = false;
 
    return;
} // end of DRV8353_resetEnableTimeout() function
 
static inline void DRV8353_resetRxTimeout(DRV8353_Handle handle)
{
    DRV8353_Obj *obj = (DRV8353_Obj *)handle;
 
    obj->rxTimeOut = false;
 
    return;
} // end of DRV8353_resetRxTimeout() function
 
extern void DRV8353_setupSPI(DRV8353_Handle handle,
                             DRV8353_VARS_t *drv8353Vars);
 
extern uint16_t DRV8353_readSPI(DRV8353_Handle handle,
                                const DRV8353_Address_e regAddr);
 
extern void DRV8353_writeSPI(DRV8353_Handle handle,
                             const DRV8353_Address_e regAddr,
                             const uint16_t data);
 
extern void DRV8353_writeData(DRV8353_Handle handle,
                              DRV8353_VARS_t *drv8353Vars);
 
extern void DRV8353_readData(DRV8353_Handle handle,
                             DRV8353_VARS_t *drv8353Vars);
 
//*****************************************************************************
//
// Close the Doxygen group.
//
//*****************************************************************************
 
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
 
#endif // end of DRV8353_H definition